IEEE Project Abstract

State-of-the-art CMOS- based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1~1.2V).The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100~300pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40nm CMOS process achieves a with in wafer σ/μ of 0.204 and a TC of 18ppm/°C with a power consumption of 4.2nW.