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IEEE Final Year Project Topic for CSE

Base Paper Title

A Novel DSP Architecture for Scientific Computing and Deep Learning

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IEEE Project Abstract

Exascale computing requires accelerators with ultrahigh power efficiency. Digital signalprocessors (DSPs), the most important embedded processors widely known for high power efficiency, arerarely explored in the HPC community. We propose a 64-bit general purpose DSP architecture, FTMatrix2000, which not only integrates main features of DSPs, but also presents several novel enhancementsfor scientific computing. The FT-Matrix2000 architecture comprises multiple FT-Matrix2 cores andoptional RISC CPU cores. The FT-Matrix2 core utilizes a VLIW+SIMD architecture, provides support fordouble precision operations, and optimizes both the data and control path for scientific computing. Ourevaluations show that the performance and efficiency of FT-Matrix2000 are 1107GFLOPS and 92.25%.Compared with the MIC and a 40nm process GPU, FT-Matrix2000 improves the GEMM power efficiencywith a factor of 1.49 and 2.68, respectively. We build up a prototype supercomputer with FTMatrix2000/12. Its HPL efficiency achieves 62.2%, and the performance power ratio is 5.33 GFLOPS/W,which can rank the fourth in the latest Green500 list. These results validate that the FT-Matrix2000architecture is suitable for scientific computing while maintaining the efficiency of signal processing well.Moreover, the enhancement of FT-Matrix2000 in vector and matrix related computations also enable it toefficiently support deep learning related applications. We have implemented some typical DCNN modelson FT-Matrx2000, NVIDIA GPUs and Vision P6 DSP. Experiments demonstrate that the averagecomputation efficiency of the proposed architecture based on Matrix2000 is about 20∼35% and 8% higherrespectively than GPUs and Cadence Vision P6 DSP.

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