True random number generators (TRNGs) are widely used in cryptographic systems, and their security is the base of many cryptographic algorithms and protocols. At present,entropy estimation based on a stochastic model is a well recommended approach to evaluate the security of a specific TRNG structure. Besides, the generation speed is also an important property for TRNGs. For this purpose, analog-to-digital converter (ADC) can be employed to sample the noisy signal to achieve high bit rate. However, no research focuses on the entropy estimation on the basis of the stochastic model towards ADC sampling. In this paper, we propose an entropy estimation for the ADC sampling based TRNG through extending an existing model. In particular, we present an equivalent model to estimate the entropy of any single bit in converted sample obtained by ADC sampling. Furthermore, we propose a method of the entropy estimation for multi-bit ADC output, which provides the lower bound of the entropy. By conducting simulations and hardware experiments on this type of TRNG, we confirm the correctness of the proposed entropy estimation theory. The prototype chip is fabricated in SMIC 65 nm process, and the consumed power is34 mW. The random bit sequences compatible with the AIS 31 standard are generated at a speed of 132.3 Mbps. The sequences are able to pass rigorous statistical test suites including NIST SP800-22, Diehard and TestU01 (containing Big Crush test) after simple post-processing at a bit rate of around 33 Mbps.
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